PD IEC TR 61189-5-506:2019

What is PD IEC TR 61189-5-506 - Surface insulation resistance (SIR) testing of solder fluxes about?

PD IEC TR 61189-5-506 is the fifth part of the international standard used for Test methods for electrical materials, printed boards other interconnection structures and assemblies. This methods helps in intercomparison evaluation to implement the use of fine pitch test structures for surface insulation resistance (SIR) testing of solder fluxes.

PD IEC TR 61189-5-506 is an intercomparison supporting the development of IEC 61189-5-501 in relation to the SIR method.

PD IEC TR 61189-5-506 sets out to validate the introduction of a new 200-μm gap SIR pattern and was benched marked against existing SIR gap patterns of 318 μm and 500 μm.

Who is PD IEC TR 61189-5-506 - Surface insulation resistance (SIR) testing of solder fluxes for?

PD IEC TR 61189-5-506 on Test methods for electrical materials, printed boards and other interconnection structures and assemblies is useful for:

• Manufacturers of electronic devices
• Electrical engineers
• Manufacturers of printed boards
• Research Laboratories

Why should you use PD IEC TR 61189-5-506 - Surface insulation resistance (SIR) testing of solder fluxes?

Surface insulation resistance (SIR) is the electrical resistance of insulating material between a pair of conductors, or grounding devices. That is determined under specified environmental and electrical conditions.

PD IEC TR 61189-5-506 helps in reducing the corrosion issues and the problems of electromechanical (ECM) migration in electric materials and boards. The surface insulation resistance (SIR) test is useful in characterizing the flux residues in terms of electromechanical (ECM). The surface insulation resistance (SIR) ensures the resistance stability by applying an electrical bias across an interdigitated comb in a damp heat environment at elevated temperatures. PD IEC TR 61189-5-506 helps in demonstrating the interoperability of different SIR patterns that result in using the 200-μm pattern. With the  help of board design mentioned in PD IEC TR 61189-5-506 is useful in constructing the printed boards. 

PD IEC TR 61189-5-506 specifies the test procedures and methods for implementing the fine pitch test structures for surface insulation resistance (SIR) testing. This test method helps in avoiding failures and is also useful in understanding the intercomparison that validates the introduction of the 200-μm gap pattern 200-μm gap SIR pattern.