BS IEC 62526:2007

What is BS IEC 62526 - Extensions to standard test interface language (STIL) for semiconductor design environments about?

BS IEC 62526 is an international standard that discusses extensions to standard test interface language (STIL) for semiconductor design environments.

BS IEC 62526 outlines the structures that are defined in STIL to support usage as semiconductor simulation stimulus, including:

• Mapping signal names to equivalent design references
• The interface between scan and built-in self-test (BIST) and the logic simulation
• Data types to represent unresolved states in a pattern
• Parallel or asynchronous pattern execution on different design blocks
• Expression-based conditional execution of pattern constructs

Structures are defined in STIL to support the definition of test patterns for sub-blocks of a design (i.e., embedded cores) such that these tests can be incorporated into a complete higher-level device test.

Structures are defined in STIL to relate failed information from device testing environments back to the original stimulus and design data elements.

Note: Syntax in  BS IEC 62526 is used in the definition of patterns for sub-blocks.

Who is BS IEC 62526 - Extensions to STIL for semiconductor design environments for?

BS IEC 62526 on extensions to standard test interface language (STIL) for semiconductor design environments is useful for:

• Developers of standard test interface language (STIL)
• Institutions and organisations working on standard test interface language (STIL) for semiconductor design environments
• Regulatory authorities

Why should you use BS IEC 62526 - Extensions to STIL for semiconductor design environments?

Standard test interface language (STIL) was initially developed to address the lack of a common solution for transferring digital test data from the generation environment to the test equipment.

Standard Test Interface Language (STIL) is a standard language that provides an interface between digital test generation tools and test equipment. STIL may be directly generated as an output language of a test generation tool, or it may be used as an intermediate format for subsequent processing.

BS IEC 62526 assists you with syntax description, expressions, statement structure, organization, statements, user keywords statement, variables block, signals block, signal groups block, pattern burst block, timing block, waveform table block, scan structures block, pattern data, pattern statements, procedure, macro data substitution, environment block, pragma block, and pattern fail report to improve the optimisation for extensions to standard test interface language (STIL) for semiconductor design environments.

With obedience and compliance to BS IEC 62525, you can standardize the performance of standard test interface language (STIL) in semiconductor design environments.