Around the world, engineers in industries such as electronics and automobiles are developing many kinds of systems and products. However, these are developed based on conventional design processes and suffer from many design problems and long design times. Because the laws of nature can be expressed mathematically, mathematics is a good algorithmic method for the description and modelling of such systems. Mathematical modelling is also an important approach for both solving problems and visualizing the abstract concepts involved.
A hardware description language provides a means to describe the behaviour of a system precisely and concisely. PD IEC/TR 63051 describes the main functional requirements for Mathematical algorithm hardware description languages (HDLMath) for system-level modelling and verification and compares existing HDLMath languages from the viewpoint of designers.
Confirming to PD IEC/TR 63051, HDLMath language supports a large number of mathematical system tasks, and provides access to information regarding the occurrence of overflows, underflows, maximum number of bits needed, cumulative error, etc.
PD IEC/TR 63051 on HDLMath for system modelling and verification is useful for:
Mathematical algorithm description language is used to describe and verify the entire behaviour of systems and products using mathematical algorithms of electronic systems. It is a higher-level language than conventional hardware description languages such as VHDL and System Verilog. Implementing PD IEC/TR 63051, HDLMath and its design environment can support the design of many domains and applications.
PD IEC/TR 63051 adds HDLMath to BVDL as a system modelling language. PD IEC/TR 63051 describes nine functional requirements for an HDLMath and compares current HDLMath languages from a design viewpoint.
PD IEC/TR 63051 is intended to accelerate the standardization of a mathematical algorithm design language and to establish a good system modelling environment in the world.
IEC TR 63051:2017